Manufacturing a chip or an integrated circuit may in general include various layering and patterning processes, e.g. for processing a power chip, and therefore, a plurality of alignments may be necessary during processing. According to this, the alignment marks used for the positioning of the carrier during the processes, e.g. during layering, patterning or ion implantation, may degrade during the plurality of processes; and therefore may be visible in less quality and may be detectable in less accuracy, so that the alignment marks may need to be refreshed several times during manufacturing a chip. In various processes, the alignment marks may be covered with an additional material and, therefore, may be not suitable to enable an accurate alignment. Commonly used alignment marks may not be stable at high processing temperatures, e.g. larger than 1000° C.